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rbic dlite - auto tm sensor signal conditioner with diagnostics zssc3015 datasheet ? 2016 integrated device technology, inc. 1 january 20, 2016 zssc3015 vbp vbn vss s ig ? vgate 0.1 f v supply ground +2.7 to +5.5 v out/owi vdd brief description the zssc3015 sensor signal conditioner ic is adjustable to nearly all piezo - resistive bridge sensors. measured and corrected bridge values are provided at the sig? pin, which can be configured as an analog voltage output or as a one - wire serial digital output. the zacwire? digital one - wire interface (owi) can be used for a simple pc - controlled calibration procedure to program a set of calibration coefficients into a n on - chip eeprom. the calibrated zssc3015 and a specific sensor are mated digitally: fast, precise, and without the cost overhead associated with trimming by external devices or laser. integrated diagnostics functions make the zssc3015 parti - cularly well s uited for automotive applications. features ? digital compensation of sensor offset, sensitiv ity, temperature drift, and non linearity ? programmable analog gain and digital gain; accommodates bridges with spans < 1mv/v and high offset ? many diagnostic feature s on chip (e.g., eeprom signature, bridge connection checks, bridge short detection, power loss detection) ? independently programmable high and low clipping levels ? 24- bit customer id field for module traceability ? internal temperature compensation reference (no external components) ? option for external temperature compensation with addition of single diode ? output options: rail - to - rail ratiometric analog voltage (12 - bit resolution), absolute analog voltage, zacwire? digital one - wire interface ? fast power - up to d ata out response; output available 5ms after power - up ? current consumption depends on programmed sample rate and mode: 1ma down to 300 a (typ . ) ? fast response time: 1.4ms typical ? high voltage protection: 30v with external jfet ? aec - q100 qualified benefits ? no external trimming components required ? pc - controlled configuration and calibration via zacwire? one - wire interface ? simple, low cost ? high accuracy (as high as 0.1% fso @ - 25 to 85c; 0.25% fso @ - 50 to 150c) ? single - pass calibration ? quick and precis e available support ? evaluation kit available ? mass calibration system available ? support for industrial mass calibration available ? quick circuit customization possible for large production volumes physical characteristics ? wide operation temperature: ? 50c to +150c ? supply voltage 2.7 to 5.5v; with external jfet, 5.5 to 30v ? small sop8 package zssc3015 application circuit
rbic dlite - auto tm sensor signal conditioner with diagnostics zssc3015 datasheet ? 2016 integrated device technology, inc. 2 january 20, 2016 2 1 5 6 7 8 3 4 zssc3015 bsink vbp exttemp vbn vss sig tm vdd vgate 0.1 f v supply ground +2.7 to +5.5 v out optional bsink 2 1 5 6 7 8 3 4 zssc3015 bsink vbp exttemp vbn vss sig tm vdd vgate 0.1 f v supply ground +5.5 to +30 v out optional bsink s d bss169 highly versatile applications in many markets including ? industrial ? b uilding automation ? office automation ? white goods ? automotive ? portable devices ? your innovative designs analog block digital block rbic dlite-auto zssc3015 0.1 f vss vbp 12-bit dac outbuf1 zacwire tm interface digital core eeprom with charge pump preamp inmux temperature reference voltage reference power save por/oscillator vbn vgate sig tm bsink (optional) v dd (2. 7 to 5. 5 v ) jfet 1 (optional if supply is 2 .7 to 5.5 v) d s v supply 5.5 v to 30 v sensor diagnostics exttemp power lost diagnostic a d 14-bit adc _ + ptat optional ext. diode for temp 0 v to 1 v ratiometric rail-to -rail owi/ zacwire tm zssc3015 block diagram rail - to - rail ratiometric voltage output applications absolute analog voltage output applications part ordering examples ( see section 11 in the data sheet for additional options .) sales code description package zssc3015 n e 1 b zssc3015 die ? temperature range: - 50c to +150c unsawn on wafer zssc3015 n e 1 c zssc3015 die ? temperature range: - 50c to +150c sawn on wafer frame zssc3015 n e 2t(r) zssc3015 sop8 (150 mil) ? temperature range: - 50c to +150c tube: add ? - t? to sales code . reel: add ? - r? zssc3015kit zssc3015 ssc evaluation kit: communication board, ssc board, sensor replacement board, usb cable, 5 ic s amples, instructions for downloading ssc evaluation software kit corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800- 345- 7015 or 408- 284- 8200 fax: 408 - 284- 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performa nce specifications and operating parameters of the described products are determined in an independent state and are not guarante e d to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, includin g, but not limited to, the suitability of idt's products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey an y license under intellectual property rights of idt or any thir d parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an expre ss, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt an d its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.
zssc3015 datasheet ? 2016 integrated device technology, inc. 3 january 20, 2016 contents list of figures .......................................................................................................................................................... 4 list of tables ........................................................................................................................................................... 5 1 electrical c haracteristics .................................................................................................................................. 6 1.1. absolute maximum ratings ....................................................................................................................... 6 1.2. recommended operating conditions ....................................................................................................... 6 1.3. electrical parameters ................................................................................................................................ 7 1.4. analog inputs versus output resolution ................................................................................................... 9 2 circuit description .......................................................................................................................................... 11 2.1. signal flow and block diagram ............................................................................................................... 11 2.2. analog front end ..................................................................................................................................... 12 2.2.1. bandgap/ptat and ptat amplifier ................................................................................................. 12 2.2.2. bridge supply .................................................................................................................................... 12 2.2.3. preamp block ................................................................................................................................. 12 2.2.4. analog - to - digital converter (adc) .................................................................................................... 13 2.3. digital signal processor .......................................................................................................................... 13 2.3.1. eeprom ........................................................................................................................................... 14 2.3.2. one - wire interface ? zacwire? ...................................................................................................... 15 2.4. output stage ............................................................................................................................................ 1 5 2.4.1. digital to analog converter (output dac) with programmable clipping limits ............................... 15 2.4.2. output buffer and output short circuit protec tion ............................................................................ 16 2.4.3. voltage reference block .................................................................................................................. 16 2.5. clock generator / power - on reset (clkpor) ...................................................................................... 17 2.6. diagnostic features ................................................................................................................................. 17 2.6. 1. eeprom integrity ............................................................................................................................. 18 2.6.2. sensor connection check ................................................................................................................ 18 2.6.3. sensor short check .......................................................................................................................... 19 2.6.4. power loss detection ....................................................................................................................... 19 2.6.5. exttemp connection checks ........................................................................................................... 19 3 functional description .................................................................................................................................... 20 3.1. general working mode ............................................................................................................................ 20 3. 2. normal mode sample rate ..................................................................................................................... 22 3.3. zacwire? communication interface ...................................................................................................... 23 3.3.1. properties and parameters ............................................................................................................... 23 3.3.2. bit encoding ...................................................................................................................................... 23 3.3.3. write operation from master to zssc3015 ...................................................................................... 24 3.3.4. zssc3015 read operations ............................................................................................................ 24 3.3.5. high level protocol ........................................................................................................................... 27 3.4. command/data bytes encoding ............................................................................................................. 28 3.5. calibration sequence .............................................................................................................................. 29 3.6. eeprom bits .......................................................................................................................................... 31
zssc3015 datasheet ? 2016 integrated device technology, inc. 4 january 20, 2016 3.7. calibration math ...................................................................................................................................... 34 3.7.1. correction coefficients ...................................................................................................................... 34 3.7.2. interpretation of binary numbers for correction coefficients ........................................................... 35 3.8. reading eeprom contents ................................................................................................................... 38 4 application circuit examples .......................................................................................................................... 39 4.1. three - wire rail - to - rail ratiometric output ............................................................................................. 39 4.2. absolute analog voltage output ............................................................................................................. 40 4.3. three - wire ratiometric output with over - voltage protection ................................................................ 41 4.4. digital output ........................................................................................................................................... 41 4.5. output resistor/capacitor limits ............................................................................................................. 41 5 eeprom restoration .................................................................................................................................... 42 5.1. default eeprom contents ..................................................................................................................... 42 5.1.1. 1v_trim/jfet_trim .......................................................................................................................... 42 5.2. eeprom restoration procedure ............................................................................................................ 42 6 pin configuration and package ...................................................................................................................... 44 7 esd/latch - up - protection ............................................................................................................................... 45 8 test ................................................................................................................................................................. 45 9 quality and reliability ..................................................................................................................................... 45 10 customization ................................................................................................................................................. 45 11 ordering sales codes .................................................................................................................................... 46 12 r elated documents ........................................................................................................................................ 46 13 definitions of acronyms .................................................................................................................................. 47 14 document revision history ............................................................................................................................ 48 list of figures figure 2.1 zssc3015 block diagram ................................................................................................................ 11 figure 2.2 dac output timing for highest update rate ................................................................................... 15 figure 3.1 general working mode ..................................................................................................................... 21 figure 3.2 manchester duty cycle ..................................................................................................................... 23 figure 3.3 19- bit write frame ............................................................................................................................ 24 figure 3.4 read acknowledge ........................................................................................................................... 24 figure 3.5 digital output (nom) bridge readings ............................................................................................ 25 figure 3.6 digital output (nom) bridge readings with temperature ............................................................... 25 figure 3.7 read eeprom contents ................................................................................................................. 26 figure 3.8 transmission of a number of data packets ..................................................................................... 26 figure 3.9 zacwire? output timing for lower update rates .......................................................................... 27 figure 4.1 rail - to - rail ratiometric voltage output ? temperature compensation via external diode ............ 39 figure 4.2 absolute analog voltage output ? temperature compensation via external diode with external jfet regulation ............................................................................................................................... 40 figure 4.3 ratiometric output, temperature compensation via internal ptat ................................................ 41 figure 5.1 eeprom vali dation and restoration procedure ............................................................................. 43
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 figure 6.1 zssc3015 pin - out diagram ............................................................................................................ 44 list of tables table 1.1 adc resolution characteristics for an analog gain of 6 ................................................................... 9 table 1.2 adc resolution characteristics for an analog gain of 24 ................................................................. 9 table 1.3 adc resolution characteristics for an analog gain of 48 ............................................................... 10 table 1.4 adc resolution characteristics for an analog gain of 96 ............................................................... 10 table 2.1 1v reference trim (1v vs. trim for nominal process run) ............................................................. 17 table 2.2 summary of diagnostic features ..................................................................................................... 18 table 3.1 update rate for analog output ........................................................................................................ 22 table 3.2 zacwire? parameters ..................................................................................................................... 23 table 3.3 idle time between packets versus update rate .............................................................................. 26 table 3.4 total transmission time for different update rate and output configurations .............................. 27 table 3.5 command/data bytes encoding ....................................................................................................... 28 table 3.6 zssc3015 eeprom bits ................................................................................................................. 31 table 3.7 correction coefficients ..................................................................................................................... 34 table 3.8 gain_b [13:0] weightings ................................................................................................................. 35 table 3.9 offset_b weightings ......................................................................................................................... 36 table 3.10 gain_t weightings ........................................................................................................................... 36 table 3.11 offset_t weightings ......................................................................................................................... 37 table 3.12 eeprom read order ...................................................................................................................... 38 table 6.1 zssc3015 pin configuration ............................................................................................................ 44
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 1 electrical characteris tics 1.1. absolute maximum ratings the absolute maximum ratings are stress ratings only. the zssc3015 might not function or be operable above the recommended operating conditions. stresses exceeding the absolute maximum ratings might also damage the device. in addition, extended exposure to stresses above the recommended operating conditions might affect device reliability. idt does not recommend designing to the ?absolute maximum ratings.? parameter symbol min max unit analog supply voltage v dd - 0.3 6.0 v voltages at analog i/o ? in pin v ina - 0.3 vdd+0.3 v voltages at analog i/o ? out pin v outa - 0.3 vdd+0.3 v electrostatic discharge ? human body model (see section 7 ) 4000 v storage temperature range ( 10 hours) t stor -50 150 c storage temperature range (<10 hours) t stor <10h -50 170 c 1.2. recommended operating conditions parameter symbol min typ max unit analog supply voltage to ground v dd 2.7 5.0 5.5 v analog supply voltage (with external jfet regulator) v supp 5.5 7 30 v common mode voltage v cm 1 v dda ? 1.3 v ambient temperature range 1) , 2) t amb -50 150 c external capacitance between v dd and ground c vdd 100 220 470 nf output load resistance to v ss or v dd 3) r l,out 5 k ? output load capacitance 4) c l,out 10 15 nf bridge resistance 5) , 6) r br 0. 3 100 k ? power - on rise time t pon 100 ms 1) note that the maximum eeprom programming temperature is 85c. 2) if buying die, designers should use caution not to exceed maximum junction temperature by proper package selection. 3) only needed for analog output mode; not needed for digital output mode. when a pull - down resistor is used as load resistor, the power loss detection diagnostic for loss of vss cannot be assured at rl=5k; rl=10k is recommended for this configuration. 4) using the output for digital calibration, cl,out is limited by the maximum rise time t zac , rise. see section 1.3 . 5) note: minimum bridge resistance is only a factor if using the bsink feature. the rds(on) of the bsink transistor is 8 to 10 when operating at vdd=5v. this give s rise to a ratiometricity inaccuracy that becomes greater with low bridge resistances. 6) note : minimum bridge resistance is important if using certain diagnostic features. it must be at least 0.3k at v dd =2.7v and at least 0.6k at v dd =5v for the sensor short check to function properly. for details, see section 2.6.3 .
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 1.3. electrical parameters not e: see important table notes at end of table. for p arameters marked with an asterisk * there is n o verification in mass production; the parameter is guaranteed by design and/or quality observation. parameter symbol conditions min typ max unit supply voltage v dd 2.7 5.0 5.5 v supply current (varies with update rate and output mode) i dd at slowest update rate 0.3 m a at fastest update rate 1.0 1.4 temperature coefficient ? ptat source * t cptat 20 100 ppm/k power supply rejection ratio * psrr 60 db power - on reset level por 1.4 2.6 v eeprom number write cycles n wri_eep at 85 c 100k cycles data retention t wri_eep at 100 c 10 years analog front - end (afe) leakage current ? pin s vbp and vbn i in_leak s ensor connection and short check must be disabled. see sections 2.6.2 and 2.6.3 . 10 na analog -to - digital converter (adc) adc resolution r adc 14 bit integral nonlinearity (inl) 1) inl adc based on ideal slope . 8 lsb differential nonlinearity (dnl) * dnl adc 1 lsb digital -to - analog converter (dac) and buffer for analog output max imum output current i out maximum current maintaining accuracy. 2.2 ma resolution res referenced to v dd . 12 bit absolute error e abs dac input to output. 0.2% v dd differential nonlinearity * dnl no missing codes. - 0.9 +3.0 lsb 12bit upper output voltage limit v out r l = 5 k ? . 95% v dd lower output voltage limit v out with 5k ? pull down, 0 - 1v output. 16.5mv mv output short circuit protection limit i sc depends on operating conditions. short circuit protection must be enabled via diag_cfg (eeprom word [102:100]). see section 2.4.2 . 3 20 ma analog output noise peak -to - peak v noise,pp shorted input. 5 1lsb mv
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 parameter symbol conditions min typ max unit diagnostics upper diagnostic output level v dia,h 97.5% v dd lower diagnostic output level v dia,l 2.5% v dd minimum load resistor for power loss r l,out_ps pull - up or pull - down 2) in analog output mode 5 k ? external temperature measurement exttemp signal input range v tse 150 800 mv required external temperature diode sensitivity st tse 1.9 3.25 mv/k temperature span with external temperature diode t tse_sp -50 150 c zacwire? serial interface see section 3.3.1 for specifications related to the zacwire? serial interface. system response start - up time (power - up to data output) t sta fast startup 6 8 ms response time ? analog output t resp - a update_rate = 0 0.88 1.4 3.2 ms response and transmission time for digital output t res, dig update_rate = 0 1.7 2.75 5.5 ms overall linearity error ? digital e lind bridge input to output 0.025 0.04 % overall linearity error ? analog e lina bridge input to output 0.1 0.2 % overall ratiometricity error re out 10%vdd ; n ot using bsink feature 0.025 0.1 % overall accuracy ? digital (only ic, without sensor bridge) ac outd - 25c to 85c 0.1% %fso - 50c to 150c 0.25% overall accuracy ? analog 3) , 4) (only ic, without sensor bridge) ac outa - 25c to 85c 0.35% %fso - 50c to 150c 0.5% 1) note: this is 8 lsbs for the 14 - bit analog - to - digital conversion. this results in absolute accuracy to 11 - bits on the conversion result. nonlinearity is typically better at temperatures less than 125c. 2) when using a pull - down resistor as load resistor, the power loss d etection diagnostic for loss of vss cannot be assured at rl=5k; rl=10k is recommended for this configuration. 3) not included is the quantization noise of the dac. the 12 - bit dac has a quantization noise of ? lsb = 0.61mv (@ 5v vdd) = 0.0125%. 4) analog output range 2.5% to 95%.
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 1.4. analog inputs versus output resolution the zssc3015 has a fully differential chopper - stabilized pre - amplifier with 4 programmable gain settings. the output of the pre - amplifier is input to a 14 - bit charge - balanced adc . spa n, offset, temperature, and non linearity correction are performed in the digital domain. then the resulting corrected bridge value can be output in analog form through a 12 - bit dac or as a 16 - bit serial digital packet. the resolution of the output depends on the inpu t span (bridge sensitivity) and the analog gain setting programmed. digital gains can vary from [0,32). analog gains available are 6, 24, 48, and 96. note: at higher analog gain settings, there will be higher output resolution, but the ability of the zssc3 015 to handle large offsets decreases. this is expected because the offset is also amplified by the analog gain and can therefore saturate the adc input. the following tables outline the guaranteed minimum resolution for a given bridge sensitivity range. table 1 . 1 adc resolution characteristics for an analog gain of 6 analog gain 6 input span [mv/v] allowed offset (+/ - % of span) 1 minimum guaranteed resolution [bits] min typ max 57.8 80.0 105.8 38% 12.4 50.6 70.0 92.6 53% 12.2 43.4 60.0 79.4 73% 12.0 36.1 50.0 66.1 101% 11.7 28.9 40.0 52.9 142% 11.4 21.7 30.0 39.7 212% 11.4 1) in addition to tco, tcg. table 1 . 2 adc resolution characteristics for an analog gain of 24 analog gain 24 input span [mv/v] allowed offset (+/ - % of span) 1 minimum guaranteed resolution [bits] min typ max 18.1 25.0 33.1 17% 12.7 14.5 20.0 26.5 38% 12.4 7.2 10.0 13.2 142% 11.4 3.6 5.0 6.6 351% 10.4 1.8 2.5 3.3 767% 9.4 0.9 1.2 1.6 1670% 8.4 1) in addition to tco, tcg. important note: the yellow shadowed fields indicate that for these input spans with the selected analog gain setting, the quantization noise is higher than 0.1% fso.
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 table 1 . 3 adc resolution characteristics for an analog gain of 48 analog gain 48 input span [mv/v] allowed offset (+/ - % of span) 1 minimum guaranteed resolution [bits] min typ max 10.8 15.0 19.8 3% 13.0 7.2 10.0 13.2 38% 12.4 4.3 6.0 7.9 107% 11.7 2.9 4.0 5.3 194% 11.1 1.8 2.5 3.3 351% 10.4 1.0 1.4 1.85 678% 9.6 0.72 1.0 1.32 976% 9.1 1) in addition to tco, tcg. important note: the yellow shadowed fields indicate that for these input spans with the selected analog gain setting, the quantization noise is higher than 0.1% fso. table 1 . 4 adc resolution characteristics for an analog gain of 96 analog gain 96 input span [mv/v] allowed offset (+/ - % of span) 1 minimum guaranteed resolution [bits] min typ max 4.3 6.0 7.9 21% 12.7 2.9 4.0 5.3 64% 12.1 1.8 2.5 3.3 142% 11.4 1.0 1.4 1.85 306% 10.6 0.72 1.0 1.32 455% 10.1 1) in addition to tco, tcg.
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 analog block digital block rbic dlite z ssc 3015 0 . 1 f vss vbp 12 - bit dac outbuf 1 zacwire tm interface digital core eeprom with charge pump preamp inmux temperature reference voltage reference power save por / oscillator vbn vgate sig tm bsink ( optional ) v dd ( 2 . 7 to 5 . 5 v ) jfet 1 ( optional if supply is 2 . 7 to 5 . 5 v ) d s v supply 5 . 5 v to 30 v sensor diagnostics ext temp power lost diagnostic a d 14 - bit adc _ + ptat optional ext . diode for temp 0 v to 1 v ratiometric rail - to - rail owi / zacwire tm 2 circuit description 2.1. signal flow and block diagram the zssc3015 resistive bridge sensor interface ics were specifically designed as cost - effective solutions for sensing in building automation, automotive, industrial, office automation , and white goods applications. the zssc3015 emplo ys idt ?s high precision bandgap with proportional - to - absolute - temperature (ptat) output; low - power 14 - bit analog - to - digital converter (adc, a2d, a - to - d); and an on - chip digital signal processor ( dsp ) core with eeprom to precisely calibrate the bridge o utput signal. three selectable outputs, two analog and one digital, offer the ultimate in versatility across many applications. the zssc3015 rail - to - rail ratiometric analog v out signal (0v to ~5 v v out @ v dd =5v) suits most building automation and automotive requirements (12 - bit resolution). typical office automation and white goods applications require the 0 to ~1v v out signal, which in the zssc3015 is referenced to the internal bandgap. the zssc3015 is capab le of running in high - voltage (5.5 to 30 v) systems when combined with an external jfet. direct interfacing to p controllers is facilitated via idt ?s single - wire serial zacwire? digital interface. figure 2 . 1 zssc3015 block diagram
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 2.2. analog front end 2.2.1. bandgap/ptat and ptat amplifier the highly linear bandgap/ptat section provides the ptat signal to the adc, which allows accurate tempera - ture conversion. in addition, the ultra - low ppm bandgap section provides a stable voltage reference over temperature for the operation of the rest of the zssc3015 . if the bridge is not near the zssc3015, an external diode can be used for temperature measurement/compensation. the temperature signal (internal pta t or external diode) is amplified through a path in the preamp block and fed to the adc for conversion. the most significant 12 - bits of this converted result are used for temperature measurement and temperature correction of bridge readings. when temperatu re is output in digital mode, only the most significant 8 bits are given. when external temperature is selected, add a diode from the exttemp pin to ground. the diode is biased with approximately 50 a during temperature measurement cycles. the voltage leve l on exttemp is amplified through the preamp section and converted by the adc. ensure that the exttemp signal is in the range of 150mv to 800mv to prevent saturation of the adc. if the selected diode has a sensitivity in the range of 1.9mv/ o c to 3.25mv/ o c, a corrected temperature output (in digital mode) can be achieved for a 200 o c temperature span ( - 50 o c to 150 o c). 2.2.2. bridge supply the voltage - driven bridge is usually connected to v dd and ground. as a power savings feature, the zssc3015 also includes a switc hed transistor to interrupt the bridge current via pin 1 (bsink). the transistor switching is synchronized to the analog - to - digital conversion and released after finishing the conversion. to utilize this feature, the low supply of the bridge should be conn ected to bsink instead of ground. depending on the programmable update rate, the average current consumption (including bridge current) can be reduced to approximately 20%, 5% , or 1%. note this feature has no power savings benefit if using the fastest upda te rate mode. 2.2.3. preamp block the differential signal from the bridge is amplified through a chopper - stabilized instrumentation amplifier with very high input impedance designed for low noise and low drift. this pre - amp provides gain for the differential sign al and re - centers its dc to v dd /2. the output of the preamp section is fed into the adc. the calibration sequence performed by the digital core includes an auto - zero sequence to null any drift in the pre - amp state over temperature. the p re - a mp can be set t o a gain of 6, 24, 48 , or 96 through eeprom. see pamp_gain in section 3.6 . the inputs to the pre - amp from (vbn/vbp pins) can be reversed via an eeprom configuration bit. see ?flip polarity? under a2d_offset in section 3.6 .
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 ) _ / _ ( ) 1 ( _ tco t b offset raw br tcg t b gain zb ? ? + + ? ? ? ? + = ) 25 . 1 ( zb sot zb rb ? + = 2.2.4. analog - to - digital conver ter (adc) a 14 - bit 2 nd order charge - balancing adc is used to convert signals coming from the pre - amplifier. the converter, designed in full differential switched capacitor technique, is used for converting the various signals in the digital domain. this p rinciple offers the following advantages: ? high noise immunity because of the differential signal path and integrating behavior ? independence from clock frequency drift and clock jitter ? fast conversion time due to second order mode parameters of the adc can be controlled with eeprom settings given in section 3.6 . four selectable values for the zero point of the input voltage allow conversion to adapt t o the sensor?s offset parameter. with the flip polarity mode and the negative digital gain options, this results in seven possible zero point adjustments (not eight because the - 1/2,1/2 offset setting is the same regardless of gain polarity). the conversion rate varies with the programmed update rate. the fastest conversation rate is 1k samples/s. based on a best fit , the i ntegral n onlinearity (inl) is less than 4 lsb 14bit . 2.3. digital signal processor a digital signal processor (dsp) is used for proce ssing the converted bridge data as well as performing temperature correction and computing the temperature value for output on the digital channel. the digital core reads correction coefficients from eeprom and can correct for the following: ? bridge offset ? bridge gain ? variation of bridge offset over temperature (tco) ? variation of bridge gain over temperature (tcg) ? a s ingle second - order effect (sot) (second order term) the eeprom contains a single sot that can be applied to correct one and only one of the fol lowing: ? 2 nd order behavior of bridge measurement ? 2 nd order behavior of tco ? 2 nd order behavior of tcg if the sot applies to correcting the bridge reading, then the correction formula for the bridge reading is represented as a two - step process as follows: (1) (2) where: br = corrected bridge reading that is output as digital or analog on s ig ? pin zb = intermediate result in the calculations
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 )] ( _ / _ [ ) 1 ( _ tco t sot t b offset raw br tcg t b gain br + ? ? ? + + ? ? ? ? + = ] _ / _ [ )] ( 1 [ _ tco t b offset raw br tcg t sot t b gain br ? ? + + ? ? + ? ? ? + = ) _ _ ( _ t offset raw t t gain t + = br_raw = raw bridge reading from adc t_raw = raw temp reading converted from ptat signal or external diode gain_b = bridge gain term offset_b = bridge offset term offset_b_sign = sign bit for bridge offset term tcg = temperature coefficient gain tco = temperature coefficient offset ? t = ( t_raw ? t setl ) t setl = t_raw readin g at which low calibration was performed (typically 25c) sot = second order term if the sot applies to correcting the 2 nd order behavior of tco , then the formula for bridge correction is as follows: (3) if the sot applies to correcting the 2 nd order behavior of tcg, then the formula for bridge correction is as follows: (4) the bandgap reference gives a very l inear ptat signal, so temperature correction can always simply be accomplished with a linear gain and offset term. corrected temp erature reading: (5) where: t_raw = raw temperature reading converted from ptat signal or external diode offset_t = offset coefficient for temperature gain_t = gain coefficient for temperature 2.3.1. eeprom the eeprom contains the calibration coefficients for gain and offset, etc., and the configuration bits, such as output mode , update rate, etc. the zssc3015 also offers 3 user - programmable storage bytes for module traceability. when programming the eeprom, an internal charge pump voltage is used; therefore a high voltage supply is not needed. the eeprom is implemented as a shif t register. during an eeprom read, the contents are shifted 8 bits before each transmission of one byte occurs. the charge pump is internally regulated to 12.5 v, and the programming time is 6ms.
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 settling time 58 s ad conversion 680 s calculation 225 s dac output occurs here dac output next update settling time 58 s ad conversion 680 s calculation 225 s see section 2.6.1 regarding eeprom signatures for verifying eeprom integrity. note: eeprom writing can only be performed at temperatures lower than 85 o c. 2.3.2. one - wire interface ? zacwire? the zssc3015 communicat es via a one - wire serial interface. there are different commands available for the following: ? reading the conversion result of the adc (get_br_raw, get_t_raw) ? calibration commands ? reading from the eeprom (dump of entire contents) ? writing to the eeprom (tri m setting, configuration, and coefficients) 2.4. output stage 2.4.1. digital to analog converter (output dac) with programmable clipping limits a 12 - bit dac based on sub - ranging resistor strings is used for the digital - to - analog output conversion in the analog ratiome tric and absolute analog voltage modes. options during calibration configure the system to operate in either of these modes. the design allows for excellent testabil ity as well as low power consum ption. the dac allows programming a lower and upper clipping limit for the output signal (analog and digital). see up_clip_lim and low_clip_lim in section 3.6 . the internal 14 - bit calculated bridge value is compared against the 14- bit value formed by {11,up_clip_lim[6:0],11111} for the upper limit and {00,low_clip_lim[6:0],00000} for the lower limit. if the calculated bridge value is higher than the upper l imit or less than the lower limit, the analog output value is clipped to this value; otherwise it is output as is. example for the upper clipping level: if the up_clip_lim[6:0] = 0000000, then the 14 - bit value used for the clipping threshold is 11000000011 111. this is 75.19% of full scale. since there are 7 bits of upper clipping limit, there are 127 possible values between 75.19% and 100%. therefore the resolution of the clipping limits 0.195%. example for the lower clipping level: if the low_clip_lim[6:0] = 1111111, then the 14 - bit value used for the clipping threshold is 00111111100000. this is 24.8% of full scale. since there are 7 bits of lower clipping limit, there are 127 possible values between 0 and 24.8%. therefore the resolution of the lower clipp ing limit is 0.195%. figure 2 . 2 shows the data timing of the dac output for the update rate setting 00 . refer to the zssc3015 response time spreadsheet for details. figure 2 . 2 dac output timing for highest update rate
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 2.4.2. output buffer and output short circuit protection a rail - to - rail op amp configured as a unity gain buffer can drive resistive loads (whether pull - up or pull - down) as low as 5k ? and capacitances up to 15nf (for pure analog output). in addition, to limit the error due to amplifier offset voltage, an error compensation circuit is included which tracks and reduces offset voltage to < 1mv. the output of the zssc3015 output can be pe rmanently shorted to vdd or vss without damaging the device. the output driver contains a current - limiting block that detects a hard short and limits the current to a safe level. the output short circuit protection current can vary from a minimum of 3ma to a maximum of 20ma depending on operating conditions. output short circuit protection can be enabled via diag_cfg (eeprom [102:100]). enabling this protection is recommended when using the analog output. see table 3 . 6 for settings. 2.4.3. voltage reference block a linear regulator control circuit is included in the voltage reference b lock to interface with an external jfet to allow operation in systems where the supply voltage exceeds 5.5v. this circuit can also be used for over - voltage protection. the regulator set point has a coarse adjustment controlled by the jfet_cfg eeprom bits t hat can adjust the set point around 5.0 or 5.5v . (see table 3 . 6 for bit locations and section 2.3.1 regarding writing to the eeprom.). the 1v trim setting (see below) can also act as a fine adjust for the regulation set point. the 5v reference can be trimmed within +/ - 15mv. note: if using the exter nal jfet for over - voltage protection purposes (i.e., 5v at jfet drain and expecting 5v at jfet source), there will be a voltage drop across the jfet; therefore ratiometricity will be slightly compromised depending on the rds(on) of the chosen jfet. a j107 is the best choice because it has only an 8mv drop worst case. if using as regulation instead of over - voltage, a mmbf4392 or bss169 also works well. the voltage reference b lock uses the absolute reference voltage provided by the bandgap to produce two regu lated on - chip voltage references. a 1v reference is used for the output dac high reference when the part is configured in 0 - 1v analog output mode. for this reason, the 1v reference must be very accurate and includes trim so that its value can be trimmed wi thin +/ - 3mv of 1.00v. the 1v reference is also used as the on - chip r eference for the jfet regulator . the regulation set point of the jfet regulator can be fine - tuned using the 1v trim. the reference trim setting is selected with the 1v_trim/jfet_trim bit s in eeprom. see table 3 . 6 for bit locations. table 2 . 1 shows the order of trim codes with 0111 for the lowest reference voltage and 1000 for the highest reference voltage. important: optimal reference trim is determined during wafer - level testing and final package testing. back - up copies of these bits are stored in bits in the cust_id0 bits for applications requiring accurate references. in this case, see section 5 for important notes and instructions for verifying the integrity of the 1v_trim/jfet_trim bits and if necessary, restoring the value from the cust_id0 bits before calibration.
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 table 2 . 1 1v reference trim (1v vs. trim for nominal process run) order 1vref/ 5vref_trim3 1vref/ 5vref_trim2 1vref/ 5vref_trim1 1vref/ 5vref_trim0 highest reference voltage 1 0 0 0 ? 1 0 0 1 ? 1 0 1 0 ? 1 0 1 1 ? 1 1 0 0 ? 1 1 0 1 ? 1 1 1 0 ? 1 1 1 1 ? 0 0 0 0 ? 0 0 0 1 ? 0 0 1 0 ? 0 0 1 1 ? 0 1 0 0 ? 0 1 0 1 ? 0 1 1 0 lowest reference voltage 0 1 1 1 2.5. clock generator / power - on reset (clkpor) if the power supply exceeds 2.5v (maximum), the reset signal de - asserts and the clock generator starts operating at a frequency of approximately 570khz ( 10%). the exact value only influences the conversion cycle time and communication to the outside world but not the accuracy of signal processing. 2.6. diagnostic features the zssc3015 offers a full suite of diagnostic features to ensure robust system operation in the most ?mission - critical? applications. if the part is programmed in analog output mode, then diagno stic states are indicated by an output below 2.5% of vdd or above 97.5% of vdd. if the part is programmed in digital output mode, then diagno stic states will be indicated by a transmission with a generated parity error.
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 table 2 . 2 gives a summary of the diagnostic features, which are explain ed in detail in the following sections. eeprom settings that control diagnostic functions are given in section 3.6 . table 2 . 2 summary of diagnostic features detected fault analog diagnostic level zacwire ? diagnostic delay in detection * eeprom signature lower generates parity error 11ms after power -on ? loss of bridge positive upper generates parity error 2ms loss of bridge negative upper generates parity error 2ms open bridge connection upper generates parity error 2ms bridge input short upper generates parity error 2ms exttemp pin open lower generates parity error 300ms exttemp pin shorted to pwr/gnd lower generates parity error 300ms exttemp pin shorted to bp/bn ? upper generates parity error 3 ms loss of vdd lower transmissions stop dependent on r l and c l loss of vss upper transmissions stop dependent on r l and c l 2.6.1. eeprom integrity the contents of the eeprom are protected by an 8 - bit lfsr signature (linear feedback shift register). this sig - nature is regenerated and stored in eeprom every time eeprom contents are changed. this signature is gen - erated and che cked for a match after power - on reset prior to entering normal operation mode. if the generated signature fails to match, the part will output a diagnostic state on the output. in addition to an extensive temporal and code interlock mechanism used to prevent false writes to the eeprom, the zssc3015 offers an eeprom lock mechanism for high - security applications. when eeprom bits 105:103 are programmed with ?011? or ?110,? this 3 - bit field will disable the vpp charge pump and will not allow further writes to the eeprom. 2.6.2. sens or connection check four dedicated comparators permanently check the range of the bridge inputs (bp/bn) to ensure they are within the envelope of 0.8v to 0.85 ? vdd during all conversions. the two sensor inputs have a switched ohmic path to ground and if lef t floating, would be discharged. if any of the wires connecting the bridge break, this mechanism will detect it and put the zssc3015 in a diagnostic state. this same diagnostic feature can also detect a short between bp/bn and the exttemp signal if an exte rnal diode is being used for temperature measurement. see table 2 . 2 in section 2.6 for more information. * all timings as sume nominal operating frequency of 570khz. ? assumes standard command window. if fast startup is enabled, the delay is 4ms. ? a short from exttemp to bp/bn might not be detected in some circ uit configurations.
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 2.6.3. sensor short check if a short occurs between bp/bn (bridge inputs), it would normally produce an in - range output signal and there - fore would not be detected as a fault. this diagnostic mode, if enabled, will deliberately look for such a short. after the measurement cycle of the bridge, it will deliberately pull the bp bridge input to ground for 4 sec. at the end of this 4 sec window, it will check to see if the bn input ?followed? it down below the 0.8v comparator check point. if so, a short must exist between bp/bn, and the zssc3015 will output a diagnostic state. the bridge will have a minimum of 480 sec recovery time prior to the next measurement. see table 2 . 2 in section 2.6 for more information. the bridge resistance must be taken i nto account if the sensor short diagnostic feature is used. at v dd = 2.7v, the minimum bridge resistance is 0.3 k ?, a nd at v dd = 5v, the minimum bridge resistance is 0.6 k ?. 2.6.4. power loss detection if the power or gnd connection to the module containing the sensor bridge and zssc3015 is lost, the zssc3015 will output a diagnostic state if a pull - up or pull - down terminating resistor greater than or equal to 5k ? is connected in the final application . t his diagnostic mode only functions when the part is configured in analog output mode. for more information, s ee table 2 . 2 in section 2.6 . 2.6.5. exttemp connection checks when external temperature is selected and connection checking is enabled, the part performs range checking on the converted temperatur e value. if the internal adc reading of the temperature is less than 1/32 of full scale or greater than 63/64 of full scale then a diagnostic state is asserted. if the exttemp pin is shorted to ground, the adc reads less than 1/32. because 100 a is sourced onto the exttemp pin during conversions, it naturally pulls up during these times. if the exttemp pin is open, it produces an adc reading greater than 63/64 of full scale. both these bad connection conditions would be detected and result in a diagnostic o utput. if internal temperature is selected or sensor connection check is not enabled, then this diagnostic check is not enabled. see table 2 . 2 in section 2.6 for more information.
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 3 functional description 3.1. general working mode the command/data transfer takes place via the one - wire s ig ? pin u sing the zacwire tm serial communication protocol. after power - on, the zssc3015 provides a command window for 3.5ms or 10ms. (the command window length depends on the setting of the fast_startup eeprom bit ; see section 3.6 ). during the command window, the zssc3015 is waiting for a start_cm command. without this command, the normal operation mode (nom) starts. in this mode, raw bridge values are conver ted and the corrected values are presented on the output in analog or digital format (depending on the configuration stored in eeprom). if the zssc3015 receives the start_cm command during the command window, it remains in command mode (cm). the cm allows changing to one of the other modes via command. (see section 3.4 for command encoding.) if the start_r m command is sent , the zssc3015 enters the raw mode (rm) . without correc tion, the raw values are transmitted to the digital output in a predefined order. the rm can only be stopped by a power down . raw mode is used by the calibration software for collection of raw bridge and temperature data so the co rrection coefficients can be calculated. if diagnostic features are enabled and a diagnostic fault is detected, diagnostic states are indicated as follows depending on the programmed mode: ? in analog output mode: diagnostic states are indicated by an outpu t below 2.5% of vdd or above 97.5% of vdd. ? in digital output mode: diagnostic states will be indicated by a transmission with a generated parity error. for more details , see section 2.6 .
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 normal operation mode start_nom power on command mode raw mode no commands possible. measurement cycle. conditioning calculations (corrected bridge and temperature values). depending on the configuration, the sig tm pin is - 0 v to 1 v; - rail-to-rail ratiometric; - digital output diagnostic functions. measurement cycle stopped. full command set. command routine will be processed after each command measurement cycle. sig tm pin provides raw bridge and temperature values in the format: - bridge_high (1 st byte) - bridge_low (2 nd byte) - temp (3 rd byte) start_rm command window (3.5ms or 10ms); send start_cm start_cm no command power off diagnostic state* error detection figure 3 . 1 general working mode * see section 2.6 .
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 3.2. normal mode sample rate when the zssc3015 is in normal operation mode, the output rate depends mainly on the settings for the u pdate r ate and output mode. table 3 . 1 shows the nominal sample rate for analog output across u pdate r ate settings for analog o utput m ode . see section 3.3.4 for information on reading the zssc3015 and the overall update and transmission time when in d igital m ode. the average response time shown in table 3 . 1 accounts for 1.5 samples at nominal frequency and temperature. the worst - case response time accounts for process and temperature deviation on the oscillator. the worst case only occurs if the input changes immediately p rior to a special measurement. see the zssc3015 response time spreadsheet for details on the average and worst - case response time depending on the zssc3015 configuration. table 3 . 1 update rate for analog output update rate setting sample rate average response time worst case response time unit 00 0.96 1.44 3.3 ms 01 4.4 6.68 15.7 ms 10 20.2 31.58 72.4 ms 11 105.2 171.02 377.4 ms
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 start bit logic 1 logic 0 stop bit 3.3. zacwire? communication interface 3.3.1. properties and parameters table 3 . 2 zacwire ? parameters parameter symbol min typ max unit comments zacwire? frequency 1) f zac 30 36 40 khz command mode or update rate = 0 or 1 7 9 10 update rate = 2 or 3 pull - up resistor (on - chip) r zac,pu 30 k ? on - chip pull - up resistor switched on during digital output mode and during command mode (first 3ms after power up) pull - up resistor (external) r zac,pu_ext 150 ? if the master communicates via a push - pull stage, no pull - up resistor is needed; otherwise, a pull - up resist or with a value of at least 150 ? must be connected. zacwire? rise time t zac,rise 5 s any user rc network included in sig? path must meet this rise time zacwire? line resistance 2) r zacload 3.9 k ? zacwire? load capacitance 2) c zac,load 0 1 15 nf voltage low level 3) v zac,low 0 0.2 v dd rail -to - rail cmos driver voltage high level 3) v zac,high 0.8 1 v dd rail -to - rail cmos driver 1) output frequency only. the master should communicate with the zssc3015 at 20khz to 52khz when it is in command mode. 2) the rise time must be t zac ,rise = 2 ? r zacload ? c zacload 5 s . if using a pull - up resistor instead of a line resistor, it must meet this specification. the absolute maximum for c zacload is 15nf. 3) no verification in mass production; the parameter is guaranteed by design and/or quality observation. 3.3.2. bit encoding figure 3 . 2 manchester duty cycle start bit = 50% duty cycle used to set up strobe time logic 1 = 75% duty cycle logic 0 = 25% duty cycle stop bit = the zac w ire? bus will be held high for 1 bit length between consecutive data packets. s ee technical note ? zacwire? communication for more details on the zacwire? protocol.
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 3.3.3. write operation from master to zssc3015 the calibrati on master sends a 19 - bit packet frame to the zssc3015 . figure 3 . 3 19- bit write frame the incoming serial signal will be sampled at a 570 khz clock rate. this protocol is very tolerant to clock skew, and can easily tolerate a wide range of baud rates. t he incoming baud ra te should be in the 8khz to 52 khz range ( 36 khz nominal). 3.3.4. zssc3015 read operations the incoming frame will be ch ecked for prop er parity on both command and data bytes, as well as for any edge time - outs prior to a full frame being received. after a command/data pair is received, the zssc3015 will perform that command. after the command has been successfully executed by the zssc301 5, it will acknowledge success by a transmission of an a5 hex byte back to the master. if the master does not receive an a5 h transmission within 130ms of issuing the command, it must assume the command was either improperly received or could not be executed . figure 3 . 4 read acknowledge p 5 4 3 2 1 0 s command byte data byte s p 2 start bit parity bit of command or data byte command bit (example: bit 2) 7 6 p 5 4 3 2 1 0 7 6 2 data bit (example: bit 2) 19-bit frame (write) s data byte s p start bit parity bit of data byte data bit (low) p 1 0 0 1 0 1 1 0 1 data bit (high) 1 data byte packet (10-bit byte a5 h ) 0
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 the zssc3015 transmits 10 - bit bytes (1 start bit, 8 data bits, 1 parity bit). during calibration and configuration, transmissions are normally either a5 hex or data. a5 hex indi cates successful completion of a command. there are two different digital output modes configurable ( digital output with temperature and digital output with only bridge data). during normal operation mode, if the part is configured for digital output of th e bridge reading, it first transmits the high byte of bridge data, followed by the low byte. the bridge data is 14 bits in resolution, so the upper two bits of the high byte are always zero - padded. there is a stop bit time between bytes in a packet. this m eans that for the time of a bit width, the signal level is high. figure 3 . 5 digital output (nom) bridge readings the second option for digital output mode is digital output bridge reading with temperature. it will be transmitted as 3 data packets. the temperature byte represents an 8 - bit temperature quantity spanning from - 50 to 150c. figure 3 . 6 digital output (nom) brid ge readings with temperature the eeprom transmission occurs in a packet with 20 data bytes, as shown in figure 3 . 7 . 2 data byte packet (digital bridge output ) p 7 6 5 4 3 2 1 0 stop s p 0 0 5 4 3 2 1 0 s data byte bridge high data byte bridge low s p 2 stop start bit parity bit of data byte data bit (example: bit 2) stop bit 3 data byte packet (digital bridge output with temperature ) p 7 6 5 4 3 2 1 0 stop s p 0 0 5 4 3 2 1 0 s data byte bridge high data byte bridge low p 7 6 5 4 3 2 1 0 stop s data byte temperature
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 figure 3 . 7 read eeprom contents 20 data byte packet ( read eeprom ) p 7 6 5 4 3 2 1 0 p stop s 3 stop s p s stop s p 7 6 5 4 3 2 1 0 7 6 5 4 5 4 3 2 1 0 1 0 1 0 0 1 0 1 ... eeprom byte 19 data byte a 5 h eeprom byte 18 eeprom byte 2 eeprom byte 1 there is a variable idle time between packets. this idle time varies with the update rate setting in eeprom. figure 3 . 8 transmission of a number of data packets table 3 . 3 shows the idle time between packets versus the update rate. this idle time can vary by nominal +/ - 15% between parts and over a temperature range of - 50 to 150 o c. the idle time is extended by the time of one conversion at each special measurement. table 3 . 3 idle time between packets versus update rate update rate setting idle time between packets idle time at special measurements every (xx) packets 00 1ms 1.83ms (128) 01 4.33ms 5.16ms (64) 10 20.3ms 21.1ms (16) 11 106ms 107ms (8) transmissions from the zssc3015 occur at one of two speeds depending on the update rate programmed in eeprom. if the user chooses one of the two fastest update rates (00 bin or 01 bin ) then the baud rate of the digital transmis sion will b e 36 khz . h owever, if the user chooses one of the tw o slower update rates (10 bin or 11 bin ), then the baud rate of the digital transmission will be 9 khz . the total transmission time for both digital output configurations is shown in table 3 . 4 . s p p stop s p s p s idle time 0 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 5 4 idle time idle time 1 0 p s 2 packet transmission (this example shows 2 data packets ) stop
zssc3015 datasheet ? 2016 integrated device technology, inc. 27 january 20, 2016 table 3 . 4 total transmission time for different update rate and output configurations update rate setting baud rate* idle time transmission time ? bridge only readings transmission time ? bridge & temperature readings 00 36 khz 1.0 ms 21 bits 27.7 s 1.6 ms 32 bits 27.7 s 1.9 ms 01 36 khz 4.33 ms 21 bits 27.7 s 4.9 ms 32 bits 27.7 s 5.2 ms 10 9 khz 20.3 ms 21 bits 111.1 s 22.6 ms 32 bits 111.1 s 23.9 ms 11 9 khz 106 ms 21 bits 111.1 s 108.3 ms 32 bits 111.1 s 109.6 ms * typical values. see table 3.2 for details. for lower update rates, the output is followed by a power - down as shown in figure 3 . 9 . figure 3 . 9 zacwire? output timing for lower update rates zacwire tm output calculation 225 s settling time 58 s power - on settling 114 s power down ( determined by update rate ) adc conversion 680 s calculation 225 s zacwire tm output it is easy to program any standard microcontroller to communicate with the zssc3015. idt can provide sample code for a microchip pic ? microcontroller. 3.3.5. high level protocol the zssc3015 will listen for a command/data pair to be transmitted for the 3.5ms or 10ms (depending on the setting of the fast_startup eeprom bit ; see section 3.6 ) after the de - assertion of its internal power - on reset (por). if a transmission is not received within this time frame, then it will transition to normal operation mode (nom). in the nom, it will output bridge data in 0 - 1v analog, rail - to - rail ratiometric analog, or digital depending on how the part is currently configu red. if the zssc3015 receives a start_cm command within the first 3.5ms or 10ms after the de - assertion of por, then it will go into command mode (cm). in this mode, calibration/configuration commands will be executed. the zssc3015 will acknowledge successf ul execution of commands by transmission of a5 hex . the calibrating /configuring master will know a command was not successfully executed if no response is received within 130ms after issuing the command. once in command interpreting/executing mode, the zss c3015 will stay in this mode un til power is removed or a start_ nom (start normal operation mode) command is received. the start_cm command is used as an interlock mechanism to prevent a spurious entry into command mode on power up. the first command receiv ed within the command window must be a start_cm command to enter into command interpreting mode. any other commands will be ignored.
zssc3015 datasheet ? 2016 integrated device technology, inc. 28 january 20, 2016 3.4. command/data bytes encoding the 2 - byte command sent to the zssc3015 consists of 1 byte of command information and 1 byte of data information. regardless of whether the command requires data or not, 2 bytes must be sent. table 3 . 5 lists all the command/data pairings. (x=don ?t care.) table 3 . 5 command/data bytes encoding note: hex = hexadecimal command byte data description 00 hex xx hex read eeprom command via sig? pin. 20 hex 5x hex dac ramp test mode. gain_b[13:3] contains the starting point, and the increment is (offset_b/8). the increment will be added every 125 sec. 30 hex wd hex w = what d = data trim/configure: 3 rd nibble determines what is trimmed/configured. the 4 th nibble is data to be programmed. 3 rd nibble 4 th nibble data description 0 hex d hex program eeprom bits [2:0] zmdi_cfg ** . least significant 3 bits are used. 1 hex d hex trim 1v reference. least significant 4 bits of data used. 2 hex d hex offset mode. least significant 4 bits of data used. 3 hex d hex set output mode. least significant 2 bits used. 4 hex d hex set update rate. least significant 2 bits used. 5 hex d hex configure jfet regulation. 6 hex d hex program the tc_cfg register. least significant 3 bits used. most significant bit of data nibble should be 0. 7 hex d hex program eeprom bits [99:96] {sot_cfg,pamp_gain}. d hex 0x3 program eeprom bits [105:103]: eeprom locked! int. ptat used for temperature. 0x0,0x1,0x2 eeprom unlocked. int. ptat used for temperature. 0x6 eeprom locked! ext. diode used for temperature. 0x4,0x5,0x7 eeprom unlocked. ext. diode used for temperature. e hex d hex program eeprom bits [102:100] diag_cfg ?? . least significant 3 bits used. 40 hex 00 hex start _ nom => ends command mode; transition to normal operation mode. 40 hex 10 hex start_rm = start the raw mode (rm) . in this mode, if gain_b = 800 hex and gain_t = 80 hex , then the digital output will simply be the raw values of the adc for the bridge reading and the ptat conversion. 50 hex 90 hex start_cm => start the command mode; used to enter the command i nterpret ing m ode. for more details, refer to section 3.8 . ** for more details, refer to section 3.6 . ?? for more details, refer to section 3.6 .
zssc3015 datasheet ? 2016 integrated device technology, inc. 29 january 20, 2016 command byte data description 60 hex yy hex program sot ( second order term) . 70 hex yy hex program t setl . (s et the msb to 0. ) 80 hex yy hex program gain_b upper 7 - bits. (set the msb to 0.) 90 hex yy hex program gain_b lower 8 - bits . a0 hex yy hex program offset_b upper 6 - bits . (set the two msbs to 0.) b0 hex yy hex program offset_b lower 8 - bits . c0 hex yy hex program gain_t . d0 hex yy hex program offset_t . e0 hex yy hex program tco . e8 hex yy hex disable eeprom lock until next reset . f0 hex yy hex program tcg . 08 hex yy hex program upper clipping limit . (set the msb to 0.) 18 hex yy hex program lower clipping limit . (set the msb to 0.) 28 hex yy hex program cust_id0 . 38 hex yy hex program cust_id1 . 48 hex yy hex program cust_id2 . 3.5. calibration sequence although the zssc3015 can work with many different types of resistive bridges, assume a pressure bridge is being used for the following discussion on calibration. for this pressure sensing application, c alibration e ssentially involves collecting raw bridge and temperature data from the zssc3015 for different known pressures and temperatures. this raw data can then be processed by the calibration master (typically a pc) to compute the coefficients, and the calculated coefficients can then be written to the zssc3015 . idt can provide software and hardware with samples to perform the calibration. there are three main steps to calibration: 1. assigning a unique identification to the zssc3015 . this identification is programmed in eeprom and can be used as an index into the database stored on the calibration pc. this database will contain all the raw values of bridge readings and temperature readings for that part, as well as the known pressure (for this application) and temperature the bridge was exposed to. this unique identification can be stored in a concatenation of the following eeprom registers: cust_id0, cust_id1, cust_id2. these registers can also form a permanent serial number. 2. data co llection. data collection involves getting raw data from the bridge at different known pressures and temperatures. this data is then stored on the calibration pc using the unique identification of the zssc3015 as the index to the database. 3. coefficient calc ulation and write. after enough data points have been collected to calculate all the desired coefficients then the coefficients can be calculated by the calibrating pc and written to the zssc3015 .
zssc3015 datasheet ? 2016 integrated device technology, inc. 30 january 20, 2016 step 1 ? assigning unique identification assigning a uniqu e identification number is as simple as using the commands program cust_id0, program cust_id1 and program cust_id2. these three 8 - bit registers allow for more than 16 million unique devic es . step 2 ? data collection the number of unique (pressure, temperature) points that calibration must be performed at depends on the us er?s needs. the minimum is a 2 - point calibration, and the maximum is a 5 - point calibration. to acquire raw data from the part, set the zssc3015 to en ter raw mode. this is done by issuing a start_cm (start command mode 5090 hex ) command/data pair to the zssc3015 followed by a start_rm (start raw mode 4010 hex ) command/data pair. now if the gain_b term has been set to unity (800 hex ) and the gain_t term has been set to unity (80 hex ), then the part will be in the raw mode and will output raw data on its sig? pin instead of corrected bridge and temperature. capture several of these data points with the user?s calibration system ( capturing 16 each of bridge and temperature raw measurements is recommended) and average them. for highest accuracy , start gathering calibration data after the first special measurement has been completed. store these raw bridge and temperature settings in the database along with the kn own pressure and temperature. the output format during raw mode is bridge_high, bridge_low, temp. each of these is an 8 - bit quantity. the upper 2 - bits of bridge_high are zero - filled. the temp data (8 bits only) would not be enough information for accurate temperature calibration. therefore the upper three bits of temperature information are not given, but rather assumed known. therefore effectively 11 - bits of temperature information are provided in this mode. step 3 ? coefficient calculations the math to pe rform the coefficient calculation is very complicated and will not be discussed in detail. there is a rough overview in the ?calibration math? section. idt will provide software to perform the coefficient calculation. after the coefficients are calcula ted, the final step is to write them to the eeprom of the zssc3015. the number of calibration points required can be as few as two or as many as five. this depends on the precision desired and the behavior of the resistive bridge in use. 1. 2 - point calibrati on can be used if only a gain and offset term are needed for a bridge with no temperature compensation for either term. 2. 3 - point calibration would be used to obtain 1 st order compensation for either a tco or tcg term but not both. 3. 3 - point calibration could also be used to obtain 2 nd order correction for the bridge but no temperature compensation of the bridge output. 4. 4 - point calibration would be used to obtain 1 st order compensation for both tco and tcg. 5. 4 - point calibration could also be used to obtain 1 st order compensation for tco and a 2 nd order correction for the bridge measurement. 6. 5 - point calibration would be used to obtain both 1 st order tco correction and 1 st order tcg correction, plus a 2 nd order correction that could be applied to one and only one of the following: 2 nd order tco, 2 nd order tcg, or 2 nd order bridge.
zssc3015 datasheet ? 2016 integrated device technology, inc. 31 january 20, 2016 3.6. eeprom bits table 3 . 6 shows the bit order and default settings for the eeprom, which are programmed through the serial interface. see section 5 for important information for die/wafer customers. table 3 . 6 zssc3015 eeprom bits eeprom range description default settings notes 2:0 zmdi_cfg 0 hex zmdi_cfg[0] = oscillator frequency ? program to 0. zmdi_cfg[1] = offset_b_sign. flip the sign of the offset_b coefficient to be negative. zmdi_cfg[2] = fast_startup. change the command wind ow to be 3.5ms instead of 10ms. 6:3 1v_trim/jfet_trim ssss bin where ?s? is the part - specific factory bit setting for the reference voltage trim value. (back - up copies are stored in cust_id0 for applications re - quiring accurate references. see section 5 for impor - tant notes.) see table 2.1 in section 2.4.3 . 10:7 a2d_offset 3 hex ( n ormal polarity, positive gain; adc offset = [ - 1/2,1/2]) the upper two bits are flip polarity and invert bridge input (negative gain) respectively. if both are used in conjunction, negative offset modes can be achieved. 00 bin => n ormal polarity, positive gain 01 bin => n ormal polarity, negative gain 10 bin => f lip polarity, positive gain 11 bin => f lip polarity, negative gain the lower two bits form the adc offset selection. offset sele ction: 11 bin = > [ - 1/2,1/2] mode bridge inputs 10 bin = > [ - 1/4,3/4] mode bridge inputs 01 bin = > [ - 1/8,7/8] mode bridge inputs 00 bin => [ - 1/16,15/16] mode bridge inputs
zssc3015 datasheet ? 2016 integrated device technology, inc. 32 january 20, 2016 eeprom range description default settings notes 12:11 output_select 2 hex (rail - to - rail ratiometric output mode ) 00 bin => digital (3 bytes with parity) bridge high {00,[5:0]} bridge low [7:0] temp [7:0] 01 bin => 0 - 1v analog 10 bin => rail -to - rail ratiometric 11 bin => digital (2 bytes with parity) (no temp) bridge high {00,[5:0]} bridge low [7:0] 14:13 update_rate 2 hex (20ms (50hz)) 00 bin => 1 ms (1 khz) 01 bin => 4 ms (250 hz) 10 bin => 20 ms (50 hz) 11 bin => 100 ms (10 hz) 16:15 jfet_cfg 3 hex ( o ver - voltage protection ) 00 bin => no jfet regulation (lower power) 01 bin => no jfet regulation (lower power) 10 bin => jfet regulation centered around 5.0v 11 bin => jfet regulation centered around 5.5v (i.e., over - voltage protection) 31:17 gain_b 800 hex bridge gain (also see bits 10:7 ): gain_b[14] => multiply x 8 gain_b[13:0] => 14 - bit unsigned number representing a number in the range [0,8) 45:32 offset_b 0 hex unsigned 14 - bit offset for bridge correction . 53:46 gain_t 80 hex temperature gain coefficient used to correct ptat or exttemp reading . 61:54 offset_t 0 hex temperature offset coefficient used to correct ptat or exttemp reading . 68:62 t setl 0 hex stores raw ptat or exttemp reading at temperature in which low calibration points were taken . 76:69 tcg 0 hex coefficient for temperature correction of bridge gain term: tcg = 8 - bit magnitude of tcg term. sign is determined by tc_cfg (bits 87:85). 84:77 tco 0 hex coefficient for temperature correction of bridge offset term. tco = 8 - bit magnitude of tco term. sign and scaling are determined by tc_cfg (bits 87:85) . 87:85 tc_cfg 0 hex this 3 - bit term determines options for temperature compensation of the bridge. tc_cfg[2] => if set, tcg is negative tc_cfg[1] => scale magnitude of tco term by 8, and if sot applies to tco, scale sot by 8 tc_cfg[0] => if set, tco is negative
zssc3015 datasheet ? 2016 integrated device technology, inc. 33 january 20, 2016 eeprom range description default settings notes 95:88 sot 0 hex 2 nd order term. this term is a 7 - bit magnitude with sign. sot[7] = 1 ? negative sot[7] = 0 ? positive sot[6:0] = magnitude [0 - 127] this term can apply to a 2 nd order tcg, tco , or bridge correction. (see sot_cfg below .) 99:96 {sot_cfg, pamp_gain} 5 hex (sot applies to tc g ; pre - amp gain = 24) bits [99:98] = sot_cfg 00 bin = sot applies to bridge 01 bin = sot applies to tcg 10 bin = sot applies to tco 11 bin = prohibited bits [97:96] = pre - amp gain 00 bin => 6 01 bin => 24 (default setting) 10 bin => 48 11 bin => 96 102:100 diag_cfg 7 hex (output short circuit protection, sensor short checking, and sensor connection checking enabled) this 3 - bit term applies to diagnostic features : diag_cfg[2] ? e nable output short circuit protection diag _cfg[1] ? e nable sensor short checking diag_cfg[0] ? e nable sensor connection checking 105:103 lock_exttemp 0 hex (unlocked; internal ptat used for temperature) eeprom lock : 011 bin or 110 bin => locked all other => unlocked important: when eeprom is locked, the internal charge pump is disabled and the eeprom cann ot be programmed. bit 105 (the msb of this field) is also used for selecting external temperature measurement. 0 00, 0 01, 0 10, 0 11=>internal ptat used for temp 1 00, 1 01, 1 10, 1 11=>external diode used for temp 112:106 up_clip_lim 7f hex 7 - bit value used to select an upper clipping limit for the output. it affects both analog and digital output. the 14 - bi t upper clipping limit value is {11,up_clip_lim[6:0],11111}. 127 different clipping levels are selectable between 75.19% and 100% of vdd. 119:113 low_clip_lim 0 hex 7 - bit value used to select a lower clipping limit for the output. it affects both analog and digital output. the 14 - bit lower clipping limit value is {00,low_clip_lim[6:0],00000}. 127 different clipping levels are selectable between 0% and 24.8% of vdd.
zssc3015 datasheet ? 2016 integrated device technology, inc. 34 january 20, 2016 eeprom range description default settings notes 1 27:120 cust_id0 s s hex where ?s? is a part - specific factory bit setting. during factory test - ing, two back - up copies of the opti mal setting for the 1v_trim/jfet_trim bits are stored in [123:120] and in [127:124]. see im - portant notes in section 5 . customer id byte 0 . can be used to store a customer part identification number. caution: if the application requires accurate voltage references, do not overwrite this byte until completing the procedures in section 5 . 135:128 cust_id1 0 customer id byte 1 . can be used to store a customer part identification number. 143:136 cust_id2 0 customer id byte 2 . can be used to store a customer part identification number. 151:144 signature 8 - bit eeprom signature. generated through a lfsr ?? . this signature is checked on power - on to ensure integrity of eeprom contents. 3.7. calibration math 3.7.1. correction coefficients all terms are calculated external to the zssc3015 and then programmed to its eeprom through the serial interface. table 3 . 7 correction coefficients coefficient description offset_b_sign a sign bit to allow for positive and negative offset_b terms . gain_b gain term used to compensate span of bridge reading . offset_b offset term used to compensate offset of bridge reading . gain_t gain term used to compensate span of temp reading . offset_t offset term used to compensate offset of temp reading . ?? linear feedback shift register .
zssc3015 datasheet ? 2016 integrated device technology, inc. 35 january 20, 2016 coefficient description sot second order term. the sot can be applied as a second - order correction term for one of the following: ? bridge measurement ? temperature coefficient of offset (tco) ? temperature coefficient of gain (tcg) the eeprom bits 99:98 determine which term sot corrects . t setl raw_ptat or exttemp reading (upper 7 - bits) at low temperature at whic h calibration was performed (typically room temperature) . tcg temperature correction coefficient of bridge gain term. note: this term has an 8 - bit magnitude and a sign bit (tc_cfg[2] ). tco temperature correction coefficient of bridge offset term. note: this term has an 8 - bit magnitude, a sign bit (tc_cfg[0]), and a scaling bit (tc_cfg[1]), which can multiply its magnitude by 8. 3.7.2. interpretation of binary numbers for correction coefficients br_raw should be interpreted as an unsigned number in the set [0, 16383] with a resolution of 1. t_raw should be interpreted as an unsigned number in the set [0, 16383], with a resolution of 4. 3.7.2.1. gain_b interpretation gain_b should be interpreted as a value in the set [0, 64]. the msb (bit 14) i s a scaling bit that will m ulti ply the effect of the gain_b[13:0] term by 8. the remaining bits gain_b[13:0] represent a number in the range of [0,8) with gain_b[13] having a weighting of 4, and each subsequent bit has a weighting of ? the previous bit. table 3 . 8 gain_b [13:0] weightings bit position weighting 13 2 2 = 4 12 2 1 = 2 11 2 0 = 1 10 2 - 1 ? ? 3 2 - 8 2 2 - 9 1 2 - 10 0 2 - 11 examples: the binary number: 010010100110001 bin = 4.6489; gain_b[14] is 0, so the number represented by gain_b[13:0] is not multiplied by 8. the binary number: 101100010010110 bin = 24.586; gain_b[14] is 1, so the number represented by gain_b[13:0] is multiplied by 8.
zssc3015 datasheet ? 2016 integrated device technology, inc. 36 january 20, 2016 3.7.2.2. offset_b interpretation offset_b is a 14 - bit unsigned binary number, the offset_b_sign bit is pre - pended to the number to create a 15 - bit 2?s comp lement signed value. the bit weightings of {offset_b_sign, offset_b[13:0]} are shown in table 3 . 9 . table 3 . 9 offset_b weightings bit position weighting offset_b_sign -16384 13 8192 12 4096 11 2048 . . . 1 2 1 = 2 0 2 0 = 1 for example, the binary number 0 1111 1111 1100 bin = 4092. however, with the offset_b_sign bit set, the binary number 1 1111 1111 1100 bin = - 4. 3.7.2.3. gain_t interpretation gain_t should be interpreted as a number in the set [0,2]. gain_t[7] has a weighting of 1, and each subsequent bit has a weighting of ? the previous bit. table 3 . 10 gain_t weightings bit position weighting 7 2 0 = 1 6 2 - 1 = 0.5 5 2 - 2 = 0.25 4 2 - 3 3 2 - 4 2 2 - 5 1 2 - 6 0 2 - 7
zssc3015 datasheet ? 2016 integrated device technology, inc. 37 january 20, 2016 3.7.2.4. offset_t interpretation offset_t is an 8 - bit signed binary number in two?s complement form. the msb has a weighting of - 128. the following bits then have a weighting of 64, 32, 16 ? table 3 . 11 offset_t weightings bit position weighting 7 -128 6 2 6 = 64 5 2 5 = 32 4 2 4 = 16 3 2 3 = 8 2 2 2 = 4 1 2 1 = 2 0 2 0 = 1 for example, the binary number 00101001 bin = 41 dec . 3.7.2.5. tco interpretation tco is specified as having an 8 - bit magnitude with an additional sign bit and a scalar bit (tc_cfg). when the scalar bit is set, the signed tco is multiplied by 8. ? tco resolution: 0.175 v/v/ o c (refer enced to input ) ? tco range: 44.6 v/v/ o c ( referenced to input ) if the scaling bit is used, then the above resolution and range are scaled by 8 to give the following results: ? tco scaled resolution: 1.40 v/v/ o c ( referenced to input ) ? tco scaled range: 357 v/v/ o c ( referenced to input ) 3.7.2.6. tcg interpretation tcg is specified as an 8 - bit magnit ude with an additional sign bit (tc_cfg). ? tcg resolution: 17.0 ppm/ o c ? tcg range: 4335 ppm/ o c 3.7.2.7. sot in terpretation sot is a 2 nd order term that can apply to one and only o ne of the following: bridge non linearity correction, tco nonlinearity correction, or tcg nonlinearity correction. as it applies to bridge nonlinearity correction: ? resolution: 0.25% @ full scale ? range: +25% @ full scale to - 25% @ full scale (saturation in internal arithmetic will occur at greater negative nonlinearities.)
zssc3015 datasheet ? 2016 integrated device technology, inc. 38 january 20, 2016 as it applies to tcg: ? resolution: 0.3 ppm/( o c) 2 ? range: +/ - 38ppm/( o c) 2 as it applies to tco: 2 settings are possible. it is possible to scale the effect of sot by 8. if tc_cfg[1] is set, then both tco and sot?s contribution to tco are multiplied by 8. ? resolution at unity scaling: 1.51nv/v/( o c) 2 (referenced to input) ? range: +/ - 0.192 v/v/( o c) 2 (referenced to input) ? resol ution at 8x scaling: 12.1nv/v/(oc)2 (referenced to input) ? range: +/ - 1.54 v/v/(oc) 2 (referenced to input) 3.8. reading eeprom contents the contents of the entire eeprom memory can be read out using the read eeprom command (00 hex ). this command causes the zss c3015 to output consecutive bytes on the zacwire? interface . after each transmission, the eeprom contents are shifted by 8 bits. the bit order of these bytes is given in table 3 . 12. table 3 . 12 eeprom read order bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 1 offset_b[7:0] byte 2 gain_t[1:0] offset_b[13:8] byte 3 offset_t[1:0] gain_t[7:2] byte 4 t setl [1:0] offset_t[7:2] byte 5 tcg[2:0] t setl [6:2] byte 6 tco[2:0] tcg[7:3] byte 7 tc_cfg[2:0] tco[7:3] byte 8 sot[7:0] byte 9 lock[0] diag_cfg[2:0] sot_cfg/pamp_gain[3:0] byte 10 up_clip_lim[5:0] lock[2 :1] byte 11 low_clip_lim[6:0] up_clip_lim[6] byte 12 cust_id0[7:0] byte 13 cust_id1[7:0] byte 14 cust_id2[7:0] byte 15 signature[7:0] byte 16 a2d_offset[0] 1v_trim/jfet_trim[3:0] zmdi _cfg[2:0] byte 17 jfet_cfg[0] update_rate[1:0] output select[1:0] a2d_offset[3:1] byte 18 gain_b[6:0] jfet_cfg[1] byte 19 gain_b[14:7] byte 20 a5 hex
zssc3015 datasheet ? 2016 integrated device technology, inc. 39 january 20, 2016 2 1 5 6 7 8 3 4 zssc3015 bsink vbp exttemp vbn vss sig tm vdd vgate 0.1 f v supply ground +2.7 to +5.5 v out optional bsink 4 application circuit examples the minimum output analog load resistor is r l = 5k ? . this optional load resistor can be configured as a pull - up or pull - down. if it is configured as a pull - down, it cannot be part of the module to be calibrated because this would prevent proper operation of the zacwire ? . if a pull - down load is desired, it must be added to system after module calibration. there is no output load capacitance needed. 4.1. three - wire rail - to - rail ratiometric outpu t this example shows an application circuit for rail - to - rail ratiometric voltage output configuration with temperature compensation via an external diode. figure 4 . 1 rail - to - rail ratiometric voltage output ? temperature compensation via external diode the optional bridge sink allows a power savings of bridge current. the output voltage can be either ? rail - to - rail ratiometric analog output (ratiometric to vdd = vsupply). ? 0 to 1v analog output. the absolute voltage output reference is trimmable 1v (+/ - 2mv) in the 1v output mode via a 4 - bit eeprom field. see section 2.4.3 .
zssc3015 datasheet ? 2016 integrated device technology, inc. 40 january 20, 2016 2 1 5 6 7 8 3 4 zssc3015 bsink vbp exttemp vbn vss sig tm vdd vgate 0.1 f v supply ground +5.5 to +30 v out optional bsink s d bss169 4.2. absolute analog voltage output the figure below shows an application circuit for an absolute voltage output configuration with temperature com - pensation via external diode and external jfet regulation for all indust ry standard applications. figure 4 . 2 absolute analog voltage output ? temperature compensation via external diode with external jfet regulation the output signal range can be one of the following options: ? 0 to 1 v analog output. the absolute voltage output reference is tr immable: 1 v (+/ - 2 mv) in the 1 v output mode via a 4 - bit eeprom field (see section 2.4.3 ). ? rail - to - rail analog output. the on - chip reference for the jfet regulator block is trimmable: 5 v ( ~10 mv) in the ratiometric output mode via a 4 - bit eeprom field. (see section 2.4.3 ).
zssc3015 datasheet ? 2016 integrated device technology, inc. 41 january 20, 2016 2 1 5 6 7 8 3 4 zssc3015 bsink vbp exttemp vbn vss sig tm vdd vgate 0.1 f v supply ground +5.0 to +5.5 v out optional bsink s d j107 vishay 4.3. three - wire ratiometric output with over - voltage protection the figure below shows an application circuit for a ratiometric output configuratio n with temperature compensation via the internal ptat. in this application, the jfet is used for voltage protection. jfet_cfg (16:15) in the eeprom is configured to 5.5v. there is an additional maximum error of 8mv caused by the non - zero r on of the limiter jfet. figure 4 . 3 ratiometric output, temperature compensation via internal ptat 4.4. digital output for all three circuits, the output signal can also be digital. depending on the output select bits, the bridge signal or the bridge signal and temperature signal are sent. for the digital output, no load resistor or load capacity is necessary. no pull - down resistor is allowed. if a line resistor o r pull - up resistor is used, the requirement for the rise time must be met (< 5 s). the zssc3015 o utput includes an internal pull - up resistor of about 30 k ? . the digital output can easily be read by firmware from a microcontroller, and idt can provide th e customer with software for developing the interface. 4.5. output resistor/capacitor limits the limits for external components depend on the programmed output mode: ? pure analog output mode (calibration is done before): the only limit is the minimum load resist ance of 5 k ? . ? pure digital output mode with end - of - line calibration: the rc time constant of the zacwire? line must have a rise time 5 s. ? analog output with digital communication during calibration: the rc time constant of the zacwire? line must have a rise time 5 s. warning: any series line resistance forms a voltage divider in conjunction with the pull - up load device. if a series line resistance is needed, choose a low value relative to the pull - up load device.
zssc3015 datasheet ? 2016 integrated device technology, inc. 42 january 20, 2016 5 eeprom restoration if needed, the default settings for the zssc3015 (see table 3 . 6 ) can be r eprogrammed as described in sec tion 3 . the following sections describe ee prom content validation and handling during and/or after system assembly. important: during the sawing and dicing process, there is a possibility of the eeprom contents flipping, and prevention cannot be guaranteed. this is primarily a concern for the fac tory trim settings, which are customized to each part. if purchasing packaged parts, the eeprom contents have already been returned to their default values and this section can be ignored. the eeprom default values programmed during the different test leve ls have been selected so that customer has the option to refresh/reprogram trim bits that might have flipped during sawing or dicing. important: the eeprom lock is stored in the bit range 105:103. a value of 6 hex or 3 hex will lock the eeprom , disabling th e charge pump needed for eeprom writing. the lock may be temporarily ignored by using the eeprom force unlock command (e800 hex ) in command mode. this will re - enable the charge pump until the next reset. alternatively, the eeprom force unlock command could be issued in command mode and the lock itself may be reprogrammed in eeprom at this time. the complete contents can also be validated using the eeprom signature stored in bits [151:144], (see ?signature? in table 3 . 6 ). 5.1. default eeprom contents during the wafer level test (wafer/dice delivery) and during final test for sop8 packaged parts, the eeprom is programmed with the default values listed in the table 3 . 6 . during the wafer level test, the trim bits in 1v_trim/jfet_trim [6:3] are set to die - specific values. 5.1.1. 1v_trim/jfet_trim the 5v reference for the jfet regulation is factory trimmed during the final test to 5v15mv using the 1v_trim/ jfet_trim bit setting. the 4 - bit setting stored in eeprom bits [6:3] is copied twice to the cust_id0 bits [127:124] and [123:120] to ensure the factory settings are retained so that the customer can reprogram these values in the 1v_trim/jfet_trim bits if needed. 5.2. eeprom restoration procedure after module assembly, the eeprom content should be refreshed. if jfet regulation is not used for the cus - tomer?s application , wr ite the default values shown in table 3 . 6 to the eeprom bit range [143:7] and retain the existing values in the bit range [6:0]. if jfet regulation is required, the bit restoration procedure shown in the flow chart in figure 5 . 1 must be used to keep the factory settings that were programmed during the testing. note: the eeprom signature is re - calculated and updated after every eeprom writing.
zssc3015 datasheet ? 2016 integrated device technology, inc. 43 january 20, 2016 read eeprom check jfet_trim bits [6:3]=[127:124] check jfet_trim bits [6:3]=[123:120] y keep bits [6:3] n y keep bits [6:3] n perform new jfet_trim start cm restore factory trimming? y n write eeprom default values [143:7] check jfet_trim bits [123:120]=[127:124] n y write [123:120] to[6:3] figure 5 . 1 eeprom validation and restoration procedure
zssc3015 datasheet ? 2016 integrated device technology, inc. 44 january 20, 2016 6 pin configuration and package the standard package of the zssc3015 is an sop - 8 (3.81mm / 150 mil body) with a lead- pitch 1.27mm / 50mil. figure 6 . 1 zssc3015 pin - out diagram 1 2 3 4 8 7 6 5 bsink vbp exttemp vbn vss sig tm vdd vgate table 6 . 1 zssc3015 pin configuration pin no. name description 1 bsink optional ground connection for bridge ground. used for power savings. 2 vbp positive bridge connection 3 exttemp external diode connection 4 vbn negative bridge connection 5 vgate gate control for external jfet regulation/over - voltage protection 6 vdd supply voltage (2.7 to 5.5 v) 7 sig? zacwire? interface (analog out, digital out, calibration interface) 8 vss ground supply
zssc3015 datasheet ? 2016 integrated device technology, inc. 45 january 20, 2016 7 esd/latch - up - protection all pins have an esd protection of 4000v and a latch - up protection of 100 ma or of +8v/ ? 4v (to vss/vssa). esd protection referenced to the human body model is tested with devices in sop - 8 packages during product qualification. the esd test follows the human body model with 1.5k /100pf based on mil 883, method 3015.7. 8 test the test program is based on this datasheet. the final parameters that will be tested during series production ar e listed in the tables of section 1 . the digital part of the zssc3015 includes iddq and a scan chain with a boundary scan, which can be activated a nd controlled during wafer test. further test support for testing of the analog parts on wafer level is included in the dsp. 9 quality and reliability the zssc3015 is qualified according to the aec - q100 standard, operating temperature grade 0. a fit rate <5 fit (temp=55c, s=60%) is guaranteed. a typical fit rate of the c7a - technology, which is used for zssc3015, is 2. 7 fit. 10 customization for high - volume applications that require an upgraded or downgraded functionality compared to the zssc3015 , idt can c ustomize the circuit design by adding or removing certain functional blocks. for this customization, idt has a considerable library of sensor - dedicated circuitry blocks, which enable idt to provide a custom solution quickly. please contact idt for further information.
zssc3015 datasheet ? 2016 integrated device technology, inc. 46 january 20, 2016 11 ordering sales codes sales code description package zssc3015 n e 1 b zssc3015 die ? temperature range: - 50c to +150c unsawn on wafer zssc3015 n e 1 c zssc3015 die ? temperature range: - 50c to +150c sawn on wafer frame zssc3015 n e 2t(r) zssc3015 sop8 (150 mil) ? temperature range: - 50c to +150c tube: add ? - t? to sales code reel: add ? - r? zssc3015na 1 b zssc3015 die ? temperature range: - 40c to +125c unsawn on wafer zssc3015na 1 c zssc3015 die ? temperature range: - 40c to +125c sawn on wafer frame zssc3015na 2t(r) zssc3015 sop8 (150 mil) ? temperature range: - 40c to +125c tube: add ? - t? to sales code reel: add ? - r? zssc3015kit zssc3015 ssc evaluation kit: communication board, ssc board, sensor replacement board, usb cable, 5 ic s amples , instructions for downloading ssc evaluation software from www. idt .com kit contact idt sales for support and sales of idt ?s zssc3015 mass calibration system. 12 related documents documents marked with two asterisks (**) require a login account for access on the web. documents marked with three asterisks (***) are only available on request . document zssc3015 feature sheet zacwire? ssc evaluation kit documentation ssc evaluation kits feature sheet (includes ordering codes) zssc3015 technical note ? idt wafer dicing guidelines zsc31010, zsc31015, and zssc3015 technical note ? zacwire? ssc calibration sequence, dll and exe** zssc3015 technical note ? die dimensions and pad coordinates *** zssc3015 response time spreadsheet *** technical note ? zacwire? communication *** visit the zssc3015 product page ( www.idt.com/zssc3015 ) or contact your nearest sales office for the latest version of these documents.
zssc3015 datasheet ? 2016 integrated device technology, inc. 47 january 20, 2016 13 definitions of acronyms term description adc analog - to - digital converter afe analog front - end buf buffer cm command mode cmc calibration microcontroller dac digital -to - digital converter dnl differential nonlinearity dsp digital signal processor dut device under test esd electrostatic discharge fso full - scale output inl integrated nonlinearity lsb least significant bit mux multiplexer nom normal operation mode owi one - wire interface por power - on reset level psrr power supply rejection ratio ptat proportional to absolute temperature rm raw mode sot second order term
zssc3015 datasheet ? 2016 integrated device technology, inc. 48 january 20, 2016 14 document revision history revision date description 1.0 0 january 2 8, 201 3 first release. 1.01 - 1.02 march 2 5 , 2013 edits for timing diagrams. revision to block diagram. update s for part numbers , contact information , and imagery for cover and headers. minor edits . 1.10 may 6, 2013 addition of specifications for eeprom retention and cycles in section 1.3 . update for cover image. 1.11 july 3, 2014 update to section 1.2 regarding minimum bridge resistance values. update to section 2.6.3 regarding minim um bridge resistance values. update s for order table , product references , ?related documents? section , and idt contact information. 1.12 december 26, 2014 correction for default definition for eeprom bits 99:96 in table 3 . 6 . update for contact information. january 20 , 2016 changed to idt branding . corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800- 345- 7015 or 408 - 284- 8200 fax: 408 - 284- 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer pro ducts. the information contained herein is provided without representation or warranty of any kind, whether express or implied, in cluding, but not limited to, the suitability of idt's products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not co nvey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunct ion of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other countries . other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.

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